Specifications - Form Factor: µATX 24.4 cm. x 22.4 cm Form Factor
- CPU Support
- Socket -A (Socket 462) for AMD PGA Athlon processor at 3200 MHz and more.
- 133/166 and 200 MHz Host bus speed (uses dual clocking to obtain 266, 333 and 400 MHz FSB)
- System Memory
- Two 184-pin DDR SDRAM DIMM sockets
- Support for single-sided or double-sided DIMMs (DDR266, DDR333 and DDR400)
- Support for up to 2 GB system memory
- KM400A Chipset: VT8378 system controller and VT8235 V-Link south bridge Chipset consisting of the following
- High performance SMA North Bridge: Integrated VIA Apollo KT400 and graphics accelerator in a single chip
- 64-bit Advanced Memory controller supporting DDR333, 266 and 200 SDRAM
- External AGP 8x bus (pins may optionally be used for additional flat panel and flat panel monitor interfaces)
- V-Link south bridge chip includes UltraDMA-133 / 100 / 66 / 33 EIDE, 6 USB 2.0 Ports, AC97 / MC97 link (for audio and modem support), LPC, SMBus, Power Management, and Keyboard / PS2 mouse interfaces plus RTC / CMOS on chip
- 2.5 V Core and Mixed 3.3 V / 5 V Tolerant and GTL+I/O
- 35 x 35 m HSBGA (Ball Grid Array with Heat Spreader) package with 552 balls
- High Performance Athlon CPU Interface
- Supports Socket A (Socket 462) AMD Athlon processors
- HSTL-like 1.5 V high-speed transceiver logic signal levels
- Support independent address, data, and snoop interfaces
- 200 / 166 / 133 MHz DDR (Double Data Rate) transfer on Athlon CPU address and data buses
- Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
- Four-entry command queue to accommodate maximum CPU throughput
- Four-entry probe queue to stores probes from the system to the processor
- Twenty four-entry processor system data and control queue to store system data control commands in two separate read and write buffers for data movement in and out of processor interface
- Supports WC (Write Combining) cycles
- Sleep mode support
- System management interrupt, memory remap and STPCLK mechanism
- High Bandwidth 533 MB / Sec 8-bit -Link Host Controller
- Supports 66 MHz V-Link Host interface with total bandwidth of 533 MB/s
- Operates in 2x, 4x, and 8x modes
- Full duplex commands with separate command / strobe
- Request / Data split transaction
- Configurable outstanding transaction queue for Host to V-Link Client accesses
- Supports Defer / Defer-Reply transactions
- Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles
- Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency
- All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow
- Highly efficient V-Link arbitration with minimum overhead
- All V-Link transactions have predictable cycle length with known command /data duration
- Full Featured Accelerated Graphics Port (AGP) Controller
- Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling
- AGP v3.0 compliant with 8x transfer mode
- Pseudo-synchronous with the host CPU bus with optimal skew control
- Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
- AGP pipelined split-transaction long-burst transfers up to 1 GB/s
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (256 bytes)
- Sixteen level (quadwords) write data FIFO (128 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush / Fence commands
- Graphics Address Relocation Table (GART)
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support
- Advanced System Power Management Support
- Power down of SDRAM (CKE)
- VTT suspend power plane preserves memory data
- Suspend-to-DRAM and self-refresh power down
- Low-leakage I/O pads
- ACPI 1.0B and PCI Bus Power Management 1.1 compliant
- Advanced High-Performance DDR DRAM Controller
- Supports DDR333, DDR266, and DDR200 (PC2700, PC2100, and PC1600 DDR SDRAM)
- DRAM interface synchronous with host CPU (200 / 166 / 133 MHz) for most flexible configuration
- DRAM interface may be faster or slower than CPU by 33 MHz (pseudosynchronous with 166/133 MHz FSB clock)
- Concurrent CPU, AGP, and V-Link access
- Clock Enable (CKE) control for DRAM power reduction in high speed systems
- Allows use of either registered or unbuffered memory modules
- Supports 6 banks up to 3 GB DRAMs for registered modules (4 banks up to 2 GB for unbuffered modules) ?Mixed 1M / 2M / 4M / 8M / 16M / 32M / 64M /128M x 8 / 16 / 32 DRAMs
- Flexible row and column addresses 64-bit data width only
- 2.5 V SSTL-2 DRAM interface
- Programmable I/O drive capability for MA, MD, and command signals
- Two-bank interleaving for 16 Mbit DRAM support
- Four bank interleaving for 64 MB, 128 MB, 256 MB, 512 MB, and 1GB DRAM support
- Supports maximum 16-bank interleave (i.e. 16 pages open simultaneously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank)
- Four cache lines (16 quadwords) of CPU to DRAM write buffers
- Four cache lines of CPU to DRAM read prefetch buffers
- Read around write capability for non-stalled CPU read
- Speculative DRAM read before snoop result
- Burst read and write operation
- Burst length 4 and 8
- Supports CL 2/2.5 and 1T per command
- 1T and 2T command rate which can be specified bank by bank
- Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh)
- Integrated Graphics / Video Accelerator
- Optimized Shared Memory Architecture (SMA)
- 8 / 16 / 32 / 64 MB frame buffer using system memory
- Internal AGP 8x performance
- Separate 128-bit data paths between north bridge and graphics core for pixel data flow and texture / command access
- Graphics engine clocks up to 133 MHz decoupled from memory clock
- High quality DVD video playback
- Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation
- 128-bit 2D graphics engine
- 128-bit 3D graphics engine
- Floating point triangle setup engine
- 3M triangles/second setup engine
- 133M pixels/second trilinear fill rate
- Extensive Display Support
- CRT display interface with 24-bit true-color RAMDAC up to 250 MHz pixel rate with gamma correction capability
- Direct TFT flat panel interface up to 24-bit data width supporting 18, 24, 18 + 18 and 24 + 24 TFT panels or LVDS encoders
- 12-bit DVI 1.0-compatible interface for drive of flat panel monitor using external TMDS encoders
- Interface to external TV Encoder for NTSC or PAL TV display
- Support for CRT resolutions up to 1920 x 1440 and panel resolutions up to 1600 x 1200
- Automatic panel power sequencing and VESA DPMS CRT power-down
- Dual view capability where CRT and Flat Panel Monitor can have a different resolution and refresh rate
- Built-in reference voltage generator and monitor sense circuits
- I 2 C SerialBus and DDC Monitor Communications for CRT Plug-and-Play configuration
- Video Support
- High quality scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and vertical up-scaling and filtering for horizontal and vertical down-scaling)
- Colour space conversion
- Colour enhancement (contrast, hue, saturation, brightness and gamma correction)
- Colour and chroma key support
- Hardware sub-picture blending
- Bob /weave de-interlacing ode and advanced de-interlacing to improve video quality
- PAL /NTSC TV output capability using external TV encoder
- MPEG-2/1 Video Decoder
- Motion compensation for full speed DVD playback
- 2D Hardware Acceleration Features
- BitBLT (bit block transfer) functions
- Text function
- Bresenha line drawing /style line function
- ROP 3, 256 operation
- Color expansion
- Source and destination color keys
- Transparency mode
- Window clipping
- 8, 15 /16, and 32 BPP mode acceleration
- 3D Hardware Acceleration Features
- Microsoft DirectX 7.0 and 8.0 compatible
- OpenGL driver available
- Floating-point setup engine
- Triangle rate up to 3 million triangles per second and Pixel rate up to 133 million pixels per second for 2 texture, depth test and alpha blending
- Hardware back-face culling
- 16-bit,32-bit Z test, and 24+8 Z+Stencil test support
- Z-Bias support
- Stipple Test, Line-Pattern test, Texture-Transparence test, Alpha test support
- Edge anti-aliasing support
- Two textures per pass
- Tremendous Texture Format: 16 / 32 BPP ARGB, 1 / 2 / 4 / 8 BPP Luminance, 1 / 2 / 4 / 8 BPP Intensity, 1 / 2 / 4 / 8 BPP Palletized (ARGB), YUV 422 / 420 format
- Texture sizes up to 2048 x 2048
- High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic
- LOD-Bias support
- Vertex Fog and Fog Table
- Specular Lighting
- Alpha Blending
- High quality dithering
- ROP2 support
- Internal full 32-bit ARGB format for high rendering quality
- System balance to achieve high performance
- VT8235 Chipset
- 16-bit V-Link for high bandwidth north bridge data transfer
- Dual channel serial ATA / raid controller
- UltraDMA-133 / 100 / 66 / 33 master mode eide controller
- Integrated fast ethernet and eight port USB 2.0
- Direct sound AC97 audio, keyboard / mouse controller
- RTC, LPC, SMBUS, serial IRQ, plug and play, ACPI
- PC2001 compliant enhanced power management
- High Bandwidth 533 MB/s 8-bit V-Link Client Controller
- Supports 16-bit 66 MHz V-Link Client interface with total bandwidth of 1066 MB/s
- V-Link operates in 2x, 4x, and 8x modes and either 16-bit or 8-bit (for backwards compatibility)
- Full duplex commands with separate Strobe / Command
- Request / Data split transaction
- Configurable outstanding transaction queue for V-Link Client accesses
- Auto Client Retry to eliminate V-Link Host-Client Retry cycles
- Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link transactions
- for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow
- Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle length
- with known Command / Data duration
- Auto connect / reconnect capability and dynamic stop for minimum power consumption
- Parity checking to insure correct data transfers
- Integrated Peripheral Controllers
- Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller
- Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability
- Integrated USB 2.0 Controller with four root hubs and eight function ports
- AC-link interface for AC-97 audio codec and modem codec
- HSP modem support
- Integrated DirectSound compatible digital audio controller
- LPC interface for Low Pin Count interface to Super-I/O or ROM
- Integrated Legacy Functions
- Integrated Keyboard Controller with PS2 mouse support
- Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
- Integrated DMA, timer, and interrupt controller
- Serial IRQ for docking and non-docking applications
- Fast reset and Gate A20 operation
- UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE (Parallel ATA) Controller
- Dual channel master mode hard disk controller supporting four Enhanced IDE devices
- Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface
- Increased reliability using UltraDMA-133/100/66 transfer protocols
- Thirty-two levels (double words) of prefetch and write buffers
- Dual DMA engine for concurrent dual channel operation
- Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
- Full scatter gather capability
- Support ATAPI compliant devices including DVD devices
- Support PCI native and ATA compatibility modes
- Complete software driver support
- Fast Ethernet Controller
- High performance PCI master interface with scatter / gather and bursting capability
- Standard MII interface to external PHYceiver
- 1 / 10 / 100 MHz full and half duplex operation
- Independent 2K byte FIFOs for receive and transmit
- Flexible dynamically loadable EEPROM algorithm
- Physical, Broadcast, and Multicast address filtering using hashing function
- Magic packet and wake-on-address filtering
- Software controllable power down
- Universal Serial Bus Controller
- USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible
- USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible
- Eighteen level (doublewords) data FIFO with full scatter and gather capability
- Four root hubs and eight function ports
- Integrated physical layer transceivers with optional over-current detection status on USB inputs
- Legacy keyboard and PS/2 mouse support
- Direct Sound Ready AC97 Digital Audio Controller
- AC-Link access to 4 CODECs (AC97 + AMC97 + MC97)
- Multichannel Audio
- Bus Master Scatter / Gather DMA
- Dedicated read and write channels supporting simultaneous stereo playback and record
- Dedicated read and write channels supporting simultaneous modem receive and transmit
- 1 stereo DirectSound channel with source / volume control / mixer
- 1 shared FM / SPDIF PCM read channel
- 1 dedicated channel supporting multi-channel audio
- 32-byte line-buffers for each SGD channel
- Programmable 8-bit / 16-bit mono / stereo PCM data format support
- AC97 2.1 compliant
- System Management Bus Interface
- Host interface for processor communications
- Slave interface for external SMBus masters
- Concurrent PCI Bus Controller
- 33 MHz operation
- Supports up to six PCI masters
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e. allow PCI masters from both PCI buses active at the same time
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132 MB/s (north bridge data transfer via high speed V-Link)
- PCI master snoop ahead and snoop filtering
- Eight DW of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Four lines of post write buffers from PCI masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
- Delay transaction from PCI master accessing DRAM
- Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized system performance
- Complete steerable PCI interrupts
- PCI-2.2 compliant, 32 bit 3.3 V PCI interface with 5 V tolerant inputs
- Sophisticated PC2001-Compatible Mobile Power Management
- Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
- ACPI v2.0 and APM v1.2 Compliant
- CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
- PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
- Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
- suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
- Multiple suspend power plane controls and suspend status indicators
- One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
- Normal, doze, sleep, suspend and conserve modes
- Global and local device power control
- System event monitoring with two event classes
- Primary and secondary interrupt differentiation for individual channels
- Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for
- system wake-up
- 32 general purpose input ports and 32 output ports
- Multiple internal and external SMI sources for flexible power management models
- Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
- Thermal alarm on external temperature sensing circuit
- I/O pad leakage control
- Plug and Play Controller
- PCI interrupts steerable to any interrupt channel
- Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio
- Microsoft Windows XP TM , Windows NT TM , Windows 2000 TM , Windows 98 TM and plug and play BIOS compliant
- Built-in NAND-tree pin scan test capability
- 0.22 um, 2.5 V, low power CMOS process
- Single chip 27 x 27 mm, 1.0 mm ball pitch, 539 pin BGA
I/O controller: WINBOND W83697HF I/O Controller with the following features - PS/2 Keyboard and Mouse controller
- Floppy disk controller supporting one FDD with 360 KB, 720 KB, 1.2 MB and 1.44 MB
- 2 serial ports, both 16C550 Fast UART compatible.
- 1 Parallel port supporting SPP (Standard parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Capabilities Port) modes
- 1 Fan controller
Audio Chipset: Audio Subsystem for AC'97 processing using the Realtek ALC655 codec - DirectSound AC'97 2.2 Audio
- Inputs and Outputs: Stereo inputs for Line-in, CD audio, Auxiliary, mono inputs for microphone
- Mixer Features: mixer with stereo for Line, CD audio, auxiliary, music synthesizer, digital audio (wave files), and mono for microphone and speaker phone
- Features: 3D stereo enhancement for simulated surround, power management support
- Stereo microphone input with integrated preamp for enabling a 2-channel mic array
Connectors
- 1 AGP slot with integrated retention mechanism
- 2 PCI +1 Combo PCI/CNR slot
- 1 DB9 serial port (COM A )
- 1 Header serial port (COM B )
- 1 DB15 VGA port
- 1 DB25 parallel port with SPP, ECP, EPP bidirectional modes
- PS/2 keyboard and PS/2 mouse ports (not swappable)
- 6 USB 2.0; 2 rear ports + 2 front USB + 2 interne
- 1 mono microphone input (Mic-In)
- 1 Line-In
- 1 Line-Out
- 2 IDE connectors
- 1 Floppy connector
- Panel connector
- 1 RJ45 connector
Winbond BIOS Specifications
- Plug and Play
- Advanced Configuration and Power Interface (ACPI) 1.0
- Advanced Power Management (APM) 1.2
- Y2K
- PC 2001
- S3/S1 mode
- Desktop Management Interface (DMI)
- 2 Mbits flash device
- Language supported: English
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6th July 2006, 08:16 PM
) The thing is, i don't know how to get into it to disable it 
Everywhere i look i get told 'consult your PC manual' which i aint got & don't even think i've ever had one?
................... my xbox live gamertag is Nagareboshi 
As for the PC details for anyone else who can help, I've got a:
I Take it this is my motherboards info lol! Thanks alot mucho appriecio fella, take it the info i needed was:
Linear Mode
